Abstract

Most of the improvements in the performance of digital systems have been brought about by recent advanced in VLSI technology. High-level Synthesis (HLS) is a major part of VLSI design process. Its techniques can be used to yield an optimal result in the design. Yet, major applications of HLS methods are on digital filters or DSP circuits. Arithmetic in these circuits are real, integer or complex. The major theme of this thesis is to show that HLS methodologies can be applied in the design of arithmetic circuits dealing with finite field elements, such as Galois Field ${\rm GF}(2\sp{m}).$ A case study for such a design is versatile time-domain Reed-Solomon RS(n,k) decoders. The structure of the time-domain RS decoder is simple and modular which makes it fit for VLSI implementation. The first part of the thesis studies HLS and introduces a Computer-Aided-Design (CAD) tool which can be used for designing an arithmetic based circuitry such as digital filters and algebraic codes. The RS(n,k) decoding algorithm, dealing with ${\rm GF}(2\sp{m})$ (7), is modified by applying some HLS techniques as transformation, clustering and loop unfolding. The transformed algorithm is then coded in VHDL and synthesized using Synopsys tools. The area and speed of RS(n,k) decoders are estimated and simulated for different values of m. The results proved to yield an efficient, fast with maximal throughput design