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An Observable Data Cache Model for FPGA Prototyping

Title:

An Observable Data Cache Model for FPGA Prototyping

Ravishankar, Parthasarathy (2013) An Observable Data Cache Model for FPGA Prototyping. Masters thesis, Concordia University.

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Abstract

This work presents design of a configurable and observable model of L1 data cache memory and a novel method for integrating the model into an FPGA prototype. Embedded system software designers use in-circuit emulation on FPGA platforms to validate the functionality and performance of embedded software. Data cache, particularly L1, has a major impact of system performance, yet remains unobservable during software debugging and analysis. Our solution is to model the data cache as an on-chip hardware peripheral that can be integrated into the processor system and can display the state of the data cache at any given time. The model is synthesized on Xilinx Virtex 5 FPGA and validated using several benchmarks. The experimental results show that the model can accurately track cache hits and misses and can estimate the run time of an embedded software application with an average error of only 5.4%, and a worst case error of only 13.7%.

Divisions:Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Thesis (Masters)
Authors:Ravishankar, Parthasarathy
Institution:Concordia University
Degree Name:M.A. Sc.
Program:Electrical and Computer Engineering
Date:28 March 2013
Thesis Supervisor(s):Abdi, Samar
ID Code:977120
Deposited By: PARTHASARATHY RAVISHANKAR
Deposited On:06 Jun 2013 19:40
Last Modified:18 Jan 2018 17:43
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