Abstract

XOR gates are basic building blocks in the design of almost all kinds of digital circuits for signal processing, generation and control. The performance of the XOR gates can be a factor determining the performance of the complete circuits. In particular, XOR gates with a large number of inputs, which are often used for parallel processing, may make a major contribution to the delay of the circuits. Some reduction of the delay can be achieved but usually at the expense of the power dissipation. In this thesis, a comprehensive study of the XOR gate design is presented. Based on the study, an approach of designing multiple-input pass-transistor-logic XOR gates is proposed. This approach consists of two aspects. On one hand, the imperfect high-voltage levels, resulting from the imperfect voltage transmission by single-MOS switches, at some selected intermediated circuit nodes are used to reduce the signal swing so that the power dissipation can be minimized. On the other hand, the voltages at some circuit nodes are compensated to maximize the current capacity in order to reduce the delay. Thus, the XOR gates can be designed to have a significant higher performance, in terms of speed, than other pass-transistor-logic XOR gates and the power dissipation of the circuits can also be lowered. An example of application of this design approach is also presented in this thesis