Abstract

Arithmetic operations traditionally used fixed-point processing because it makes them less expensive. In integer and fixed-point arithmetic, multipliers are larger, slower and consume much more power than adders, which are often neglected in performance evaluation of DSP systems. In floating-point arithmetic that is not true and in this thesis we show that multipliers and adders are equally important. The thesis also emphasizes low power design. For that reason, some of the basic digital filter network structures, built with FP arithmetic units, are revisited to map their performance with different filtering functions. This thesis presents digital filter network structures' performance with different filtering functions. It presents filter network structures transformed from their original form to accommodate pipe-lined arithmetic units. These filter structures can also be implemented with fixed-point arithmetic units because of the speed advantage they provide. Several experiments, through hardware synthesis of the structures, show that FIR filter Direct form structure using an adder tree consumes less power than Direct form structure using a chain of adders and its Transposed form. They also show that for IIR filters, Direct form II using standard floating-point arithmetic units is power optimal. This research work is intended to provide designers with information on the performance of these structures with different applications in an effort to help reduce the "design gap"