Abstract

Global optimization of high speed and high integration CMOS VLSI circuit is greatly in need in deep submicron regime with respect to signal delay, chip area and power dissipation. Accurate modeling of signal path delays is of particular importance in optimization. Although circuit level simulators like SPICE produce accurate and detailed delay information, analytical delay models are required in general because of the time consuming computation in SPICE simulations. New analytical delay models for both inverter and non-inverter stage of CMOS circuit in deep submicron regime are proposed in this work. The modeling takes into account circuit topologies and ramp input effect. The models were studied for various CMOS circuits of different complexities. Simulation results show an overall 10% difference and a considerably speed-up as compared to SPICE level 3 simulator. Based on the new analytical delay model, a circuit optimization program is developed, which is aiming to provide designer first hand information on circuit delay, area and power consumption and to help designer find the optimum design among different circuit topologies and transistor sizings, especially in submicron region. The program reads in circuit description from SIS--a multi-level logic synthesis and minimization system, maps it into CMOS circuit stages, analyzes the performance and finds the optimal circuit topology and sizing according to the design criteria.