Abstract

This thesis describes a real-time, DSP implementation of a baseband OFDM system, which includes interleaving and forward error correction algorithms. Software modules representing discrete system blocks are created and sequentially called upon as needed. The software reconfigurable system is developed on a Texas Instruments TMS320C6201 Evaluation Module, which is based on a fixed-point processor. Different combinations of arithmetic precision and speed for the fixed-point operations were explored. The decisive combination was used to evaluate the accuracy of the system by plotting bit-error curves against an equivalent floating-point model. System efficiency is employed from the design stage through the use of Look-Up tables as well as cyclic shift registers. Upon implementation, the system is built using settings optimized for speed. In addition, memory management is used to ensure that critical instructions are kept on the fast on-chip memory while different access times for retrieving data on external memory were evaluated for best results. Finally, each software module is profiled to investigate and remove unnecessary latency issues. Processing efficiency is monitored by recording throughput results, which are used to calculate maximum bit-rates. Using these results, estimations are made for bit-rates achievable by higher performance processors. These estimations demonstrate that a highly flexible DSP platform can ultimately meet speed and flexibility requirements for Software Defined Radios.