Abstract

The integration of Formal Description Techniques (FDTs) in the software process enables formal validation, translation, synthesis and code generation. Message Sequence Charts (MSC) and Specification and Description Language (SDL) are two formal languages, widely used in the telecommunication industry. Generally MSC is used for the behavioral requirement specification, while SDL is used for the detailed design specification. The transition from the requirement specification to the design specification is usually performed manually; and the design has to be validated against the requirement specification. In a previous research work, researchers from the telesoft group at Concordia University devised an approach for generating SDL specifications from MSC specifications with a given target architecture. It guarantees correctness of the design, and consistency between the SDL specification and the MSC specification. The need for validation has been eliminated. Time concepts have been introduced in MSC-2000, which enables real-time requirements to be specified in MSC. Building on the existing framework, this thesis presents a new approach for translating MSCs with real-time requirements into SDL specifications. We analyzed and classified different types of time constraints and measurements. New algorithms for analyzing MSC specifications and generating SDL code were devised. We also built the tool and experimented with case studies to prove the feasibility of our approach.