Abstract

This research addresses assertion-based verification to verify Look Aside Interface (LA-1 Standard). The Look Aside interface is intended for devices located adjacent to a network processing device (NPE) that off load certain tasks from the network processor. This verification is performed in several steps. First, we added assertions within the control logic of the RTL block and then we added assertions between interfaces of RTL blocks by following the Look Aside interface design specification. We developed the simulation environment in Verilog and relevant testcases derived from the specification, in order to perform simulation and observe the assertion messages for possible firings. Each firing pinpoints an error in the RTL. For the assertion monitors the Accellera Open Verification Library (OVL) was used. Finally, we transformed the same assertions into Sugar 2.0 properties and performed the model checking of our Verilog RTL model using Rulebase, from IBM corp.