Abstract

Two important factors are motivating recent CMOS Radio Frequency Integrated Circuits (RFIC) research: freeing new bandwidth for commercial use and the appealing characteristics of CMOS technologies. Traditionally implemented in bipolar and III---V compounded semiconductors, radio frequency receivers operating on frequencies up to 40 GHz are currently being researched and implemented in CMOS. Global Positioning System (GPS), Blue Tooth, Radio Frequency ID (RFID), wireless local area network (WLAN) and Automated Highway System (AHS), is a partial list of the newly growing market of RFIC commercial products and these products share the same design concepts: low prices, highly integrated systems and low power designs. With these concepts in mind, CMOS technology becomes a strong contender and the question of CMOS suitability has been answered. Low Power CMOS chips have been successfully fabricated in both, research centers and industry. This dissertation explores the architectural and design techniques for CMOS Low Voltage Low Noise Amplifier design. The thesis studies different low voltage techniques and proposes a novel Low Voltage LNA design based on a cascade topology and a new way to control the amplifier gain and improve its linearity. Also, based on electromagnetic theory and simulation, simple techniques were proposed that increases the quality factor of on chip inductors. Detailed LNA design steps and optimization are presented with special focus on CMOS transistor design, biasing and layout optimization for RFIC applications.