Abstract

With the evolution of the Internet, the processing of packets at the routers while providing
flexibility in deploying new protocols and services at the same time has become a major concern.
Programmable forwarding elements with high processing capability have emerged as a solution.
But the main challenge is to find the optimal hardware architecture while taking into account
constraints such as different packet processing functions, task scheduling options, electrical
power consumption and providing quality-of-service (QoS) guarantees. Therefore, it is essential
to investigate methods that help in identifying limitations and bottlenecks before physical
fabrication. Having an appropriate model provides designers a progressive path to narrow the
design space and establish credible and feasible alternatives before deciding on an
implementation.
In this thesis, we propose a flexible and fast instruction accurate host-compiled simulator to
make it possible to explore wide ranges of architectures and application scenarios to find the
optimal configuration that meets given performance, throughput and latency for programmable
forwarding elements. Application developers can use the simulator as a virtual prototype to
simulate and debug their applications before hardware availability. Moreover, forwarding device
architects can use simulator to evaluate the trade-offs between different hardware/software
design decisions.