Abstract

The fields of Machine Learning and Artificial Intelligence have made great strides in the last decade due to the increasing computational power of Graphics Processing Units (GPUs). Neural networks make up for a very large portion of this research area, and come in great variety (e.g. feedforward, convolutional, etc.). Although they are inspired by the human brain, they have no biological plausibility aside from the high interconnectivity of nodes. Spiking Neural Networks (SNNs) are a step in the direction of greater biological plausibility with the use of inherently dynamic neurons.
As implied by the name, SNNs are composed of neurons that generate Boolean spikes when their accumulated input exceeds a threshold value. Thus, information is encoded in the timing of spiking events. Although they are computationally expensive to simulate with general-purpose computers, their dynamic behavior lends itself well to direct hardware implementations with very high parallelism and low power consumption.
This thesis proposes a scalable architecture for a hardware system that can be used to study the behavior of SNNs, as well as the trade-offs that result from the various design parameters. Using classic benchmark problems (i.e. MNIST classification and cart-pole stabilization), it was observed that SNNs are very robust against variations in neural parameters, but degrade quickly with mismatch in synaptic weights. An MNIST classification accuracy of 96.28% drops by < 2% for severe neural variations, but > 5% for small synaptic mismatches. Additionally, the performance is re-evaluated for several weight quantizations. Finally, the effects of router delays are observed.