References:

[1] B. Razavi, “Design of integrated circuits for optical communications,” John Wiley and Sons,
2012.
[2] L. D. Edmonds, “Electric currents through ion tracks in silicon devices,” IEEE Transactions
on Nuclear Science 45, 1998, pp 3153-3164.
[3] F. Wang, V. D. Agrawal, “Single Event Upset: An Embedded Tutorial,” 21st International
Conference on VLSI Design (VLSID 2008), 2008, pp. 429-434, doi: 10.1109/VLSI.2008.28.
[4] S. Bailey, B. Keller, G. Der-Khachadourian, “Project UPSET: Understanding and Protecting
Against Single Event Transients”. (accessed on May 2020) Available online:
https : //people.eecs.berkeley.edu/ stevo.bailey/documents/upsetf inal.pdf
[5] E. Sackinger, “Broadband Circuits for Optical Fiber Communication,” John Wiley and Sons,
2005.
[6] O. Ghasemi, “Analysis and Design of Wideband CMOS Transimpedance Amplifiers Using
Inductive Feedback”, PhD Thesis, Concordia University, 2012.
[7] B. Analui, “Signal integrity issues in high-speed wireline links: analysis and integrated system
solutions,” 2006.
[8] P. P. Dash, “A variable bandwidth, power-scalable optical receiver front-end,” Master’s Thesis,
Concordia University, 2013.
[9] M. Atef, H. Chen and H. Zimmermann, “10 Gb/s inverter based cascode transimpedance
amplifier in 40 nm CMOS technology,” 2013 IEEE 16th International Symposium on Design
and Diagnostics of Electronic Circuits Systems (DDECS), 2013, pp. 72-75, doi:
10.1109/DDECS.2013.6549791.
[10] G. Cowan, Lecture Slides on Receiver Circuits, Feb. 2020, Concordia University.
[11] I. Ozkaya et al., “A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS Fin-
FET,” in IEEE Journal of Solid-State Circuits, vol. 52, no. 12, pp. 3458-3473, Dec. 2017, doi:
10.1109/JSSC.2017.2734913.
[12] J. Proesel, C. Schow and A. Rylyakov, “25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-based
optical links in 90nm CMOS,” 2012 IEEE International Solid-State Circuits Conference, 2012,
pp. 418-420, doi: 10.1109/ISSCC.2012.6177072.
[13] M. Moayedi Pour Fard, O. Liboiron-Ladouceur and G. E. R. Cowan, “1.23-pJ/bit
25-Gb/s Inductor-Less Optical Receiver With Low-Voltage Silicon Photodetector,” in
IEEE Journal of Solid-State Circuits, vol. 53, no. 6, pp. 1793-1805, June 2018, doi:
10.1109/JSSC.2018.2804042.
[14] D. G. Toro, “Temporal Filtering with Soft Error Detection and Correction Technique for Radiation
Hardening Based on a C-element and BICS,” PhD Thesis, Universit´e de Bretagne
Occidentale, 2014.
[15] R. Baumann, “Soft errors in advanced computer systems,” in IEEE Design and Test of Computers,
vol. 22, no. 3, pp. 258-266, May-June 2005, doi: 10.1109/MDT.2005.69.
[16] M. Chen,“Single Event Effect Hardening Designs in 65nm CMOS Bulk Technology,” Master’s
Thesis, University of Saskatchewan, 2017.
[17] M. Menouni et al., “The lpGBTIA, a 2.5 Gbps Radiation-Tolerant Optical Receiver using
InGaAs photodetector,” TopicalWorkshop on Electronics for Particle Physics, Sep 2019, Santiago
de Compostela, Spain. pp.030, 〈10.22323/1.370.0030〉. 〈hal-0257251)
[18] P. Nsengiyumva, ”INVESTIGATING THE EFFECTS OF SINGLE-EVENT UPSETS IN
STATIC AND DYNAMIC REGISTERS” (2014). Master’s Theses and Capstones. 984.
https://scholars.unh.edu/thesis/984
[19] H. Puchner et al., “Elimination of Single Event Latchup in 90nm SRAM Technologies,”
2006 IEEE International Reliability Physics Symposium Proceedings, 2006, pp. 721-722, doi:
10.1109/RELPHY.2006.251342.
[20] S. DasGupta et al., “Effect of Well and Substrate Potential Modulation on Single Event Pulse
Shape in Deep Submicron CMOS,” in IEEE Transactions on Nuclear Science, vol. 54, no. 6,
pp. 2407-2412, Dec. 2007, doi: 10.1109/TNS.2007.910863.
[21] M. Turowski, A. Raman and G. Jablonski, “Mixed-Mode Simulation and Analysis of
Digital Single Event Transients in Fast CMOSICs,” 2007 14th International Conference
on Mixed Design of Integrated Circuits and Systems, 2007, pp. 433-438, doi:
10.1109/MIXDES.2007.4286199.
[22] H. Cha and J. H. Patel, “A logic-level model for α-particle hits in CMOS circuits,” Proceedings
of 1993 IEEE International Conference on Computer Design ICCD’93, 1993, pp. 538-542,
doi: 10.1109/ICCD.1993.393319.
[23] Y.Wang,W.Wang, Y. Du and B. Cao, ”Modeling and analysis of analog single event transients
in an amplifier circuit,” 2013 International Conference on Optoelectronics and Microelectronics
(ICOM), 2013, pp. 94-97, doi: 10.1109/ICoOM.2013.6626499.
[24] C. Xu, Y. Liu, X. Liao, J. Cheng and Y. Yang, ”Machine Learning Regression-
Based Single-Event Transient Modeling Method for Circuit-Level Simulation,” in IEEE
Transactions on Electron Devices, vol. 68, no. 11, pp. 5758-5764, Nov. 2021, doi:
10.1109/TED.2021.3113884.
[25] J. S. Kauppila et al., “A Bias-Dependent Single-Event Compact Model Implemented Into
BSIM4 and a 90 nm CMOS Process Design Kit,” in IEEE Transactions on Nuclear Science,
vol. 56, no. 6, pp. 3152-3157, Dec. 2009, doi: 10.1109/TNS.2009.2033798.
[26] W. G. Bennett et al., “Efficient Method for Estimating the Characteristics of Radiation-Induced
Current Transients,” in IEEE Transactions on Nuclear Science, vol. 59, no. 6, pp. 2704-2709,
Dec. 2012, doi: 10.1109/TNS.2012.2218830.
[27] S. Sayil, “Soft error mechanisms, modeling and mitigation,” Springer International Publishing,
2016.
[28] W. J. Snoeys, T. A. P. Gutierrez and G. Anelli, “A new NMOS layout structure for radiation
tolerance,” in IEEE Transactions on Nuclear Science, vol. 49, no. 4, pp. 1829-1833, Aug.
2002, doi: 10.1109/TNS.2002.801534.
[29] F. Faccio et al., “Total Dose and Single Event Effects (SEE) in a 0.25 μm CMOS Technology,”
in Proc. of the Fourth Workshop on Electronics for LHC Experiments, Rome, 21-25/9/1998,
p.119, CERN/LHCC/98-36.
[30] L. Chen and D. M. Gingrich, “Study of N-channel MOSFETs with an enclosed-gate layout in
a 0.18 μm CMOS technology,” in IEEE Transactions on Nuclear Science, vol. 52, no. 4, pp.
861-867, Aug. 2005, doi: 10.1109/TNS.2005.852652.
[31] L. Sterpone, L. Carro, M. Sonza Reorda, “On the Optimal Design of Triple Modular Redundancy
Logic for SRAM-based FPGAs,” DATE’05, Mar 2005, Munich, Germany. pp.1290-
1295. hal-00181306.
[32] F. Faccio et al., “An amplifier with AGC for the 80-Mbit/s optical receiver of the CMS digital
optical link,” in 5th Workshop on Electronics for the LHC Experiments (LEB 99), pp. 189-193,
1999.
[33] F. Faccio et al., “Single event upset tests of an 80-Mb/s optical receiver,” in IEEE Transactions
on Nuclear Science, vol. 48, no. 5, pp. 1700-1707, Oct. 2001, doi: 10.1109/23.960360.
[34] X. Zhou, P. Luo, L. He, R. Ling, “A radiation-hardened optical receiver chip, IEICE
Electronics Express,” 2019, Volume 16, Issue 2, Pages 20180910, Released January
25, 2019, [Advance publication] Released October 30, 2018, Online ISSN 1349-2543,
https://doi.org/10.1587/elex.15.20180910.
[35] M. Menouni, T. Xi, P. Gui, and P. Moreira, “A 5-Gb/s Radiation-Tolerant CMOS Optical
Receiver,” in IEEE Transactions on Nuclear Science, vol. 60, no. 4, pp. 3104-3109, Aug.
2013, doi: 10.1109/TNS.2013.2264477.
[36] R. Raut and M. N. S. Swamy, “Modern Analog Filter Analysis and Design: A Practical Approach,”
Germany, Wiley, 2011.
[37] M. Andjelkovic, A. Ilic, Z. Stamenkovic, M. Krstic and R. Kraemer, “An overview of
the modeling and simulation of the single event transients at the circuit level,” 2017
IEEE 30th International Conference on Microelectronics (MIEL), 2017, pp. 35-44, doi:
10.1109/MIEL.2017.8190065.
[38] D. Li et al., “Low-Noise Broadband CMOS TIA Based on Multi-Stage Stagger-Tuned Amplifier
for High-Speed High-Sensitivity Optical Communication,” in IEEE Transactions on
Circuits and Systems I: Regular Papers, vol. 66, no. 10, pp. 3676-3689, Oct. 2019, doi:
10.1109/TCSI.2019.2916150.