Abstract

As time passes by, there is an increase in desired computational ability. Networks on chip have been seen to facilitate communication between tightly coupled processing elements located on the same die. With said increasing computational demand, comes an increase in power consumption. As a result, approximate computing techniques are used in conjunction with networks on chip to reduce power consumption and latency. When implementing these approximate networks on chip, additional resources are required and may not have maximal use during runtime. In this work, we propose a network on chip design that maximizes resource usage irrespective of data type. This is achieved by using virtual channels that are configured depending on one of two operating modes. An accurate only mode allocates all bandwidth such that a single accurate link is active. The other operating mode is a mixed mode where the bandwidth is halved for approximate and accurate data types. If operating in this mixed Mode, a latency reduction of up to 4.2% from baseline can be realized when approximate traffic accounts for sixty-seven percent of all network traffic. The additional power requirement for this improvement is 22.6% when wide flits are used.