Abstract

Many core architectures have become instrumental in addressing the ever-increasing demand for computational power in modern computing systems. As these architectures scale to accommodate an ever-growing number of processing cores on a single chip, the need for efficient data movement within and between these cores has become a crucial concern. As chip designs become more complex, traditional electrical interconnects face limitations due to increasing power dissipation, signal integrity issues, and bandwidth constraints. Short-reach nanophotonic interconnects offer a promising alternative to overcome these challenges. Photonic Networks on Chips (PNoCs) have been demonstrated to provide high bandwidth with low latencies and low data-dependent power. However, large-scale adoption of PNoC is hampered by laser power overheads, thermal tuning, and electrical optical conversion. To meet the target bit error rate (BER), the laser source must output enough optical power to overcome the optical channel loss and limited receiver sensitivity for the silicon photonic links. In addition, several parallel applications, such as multimedia processing, have built-in tolerances for inaccuracies that allow soft errors on a chip, such as bit flips. However, there is no method to design energy efficient optical links. This thesis investigates the design of reconfigurable nanophotonic interconnects and provides a
reduction method to reduce the control complexity of the receivers and transmitters.