Abstract

The novel lattice-matched HFETs realized on an epilayer consisting of a thin In0.17Al0.83N barrier layer grown on top of an undoped GaN channel have been demonstrated over the past decade to enjoy improved stable high-frequency power characteristics compared to their famous AlGaN/GaN counterparts. This is specially thanks to employing a lattice-matched barrier enjoying substantial spontaneous polarization-induced sheet charge density.
An extensive body of research implies a significant correlation exists between electronic device technology, the level of 1/f noise, and the manifestation of generation–recombination (G-R) bulge signatures. This correlation has been shown to offer a highly sensitive foundation for reliability and further performance optimization of electronic devices. A decrease in low frequency noise (LFN) has a significant impact on oscillator phase noise and the performance of intermediate frequency (IF) amplifiers and mixers Thus, in this thesis, the low frequency drain noise-current characteristics of metallic-face InAlN/AlN/GaN heterostructure field effect transistors (HFETs) having fin structures only under the gate, while maintaining a planar structure in the access regions, are compared to those of the HFETs having fin structures stretched from source to drain. This work aims to address the possible difficulties in the performance of these devices. Evidence indicates that both device types follow the trends of carrier number fluctuation (CNF) with correlated mobility fluctuation (CMF) model of 1/f noise. Devices having fin structures just under the gate are exhibiting improved 1/f noise performance with lower drain noise-current spectral density.

Since a good gate-transconductance (Gm) linearity, specially at high gate over-drives, is essential to linear high-frequency amplifiers intended for use in modern telecommunication system (such as 6G networks), enhancing the linearity of the deeply scaled HFETs implemented on such epilayers is very much in demand. Moreover, the investigation of the on-state breakdown mechanism is beneficial for the definition and design of the safe operation area (SOA) in GaN-based high power amplifiers and switches. In this thesis, I have investigated the impact of the scaling of the gate-source length (LGS) and gate length (LG) on the DC characterises and gate-transconductance (Gm) linearity of metallic-face InAlN/AlN/GaN heterostructure field effect transistors (HFETs) having fin structures only under the gate and those having them stretched from source to drain. Evidence for both device types suggests that the downscaling of LGS and LG augments the electron velocity in the source-access region, as a result of which the higher carrier density under the gated-channel improves the maximum drain-current density but not necessarily the Gm linearity of the device. It is shown that the devices having a planar and longer source access region are exhibiting relatively improved gate-transconductance linearity. In addition, the downscaling of the LG is observed to have a positive influence on device linearity. However, the negative impact of the downscaling of the LGS and LG on the on-state breakdown voltage has been observed.
In addition, in this thesis I have investigated the effect of partially etching of the gated barrier on the Gm linearity of lattice-matched InAlN/GaN HFETs. Simulation results show an improvement in linearity observed through broadening the gate transconductance characteristics of Vth-modulated HFETs over the non-recessed and an alternative recessed HFET, for which gated barrier was uniformly recessed.