Abstract

Many-core Commercial-off-the-shelf (COTS) processors offer a promising solution
for meeting the performance and cost requirements of safety-critical avionics applications.
However, the increased transistor count in these processors makes them more prone to soft
errors, potentially leading to system failures. This raises challenges in integrating their use
in critical applications due to limited research on how to mitigate the radiation-induced
soft errors on open-source many-core processors. Various mitigation strategies have been
proposed, including hardware and software techniques. Despite these efforts, a significant
gap remains, largely due to the inefficient use of multi-core processor resources.
Our work addresses this gap by integrating Triple Modular Redundancy (TMR) into
OpenPiton, an open-source many-core processor while maintaining minimal time and area
overhead. This integration enhances the system’s robustness against soft errors, leveraging
unused cores for redundant threads, thus improving overall reliability. Our methodology
includes detailed implementation strategies for multi-threaded TMR, addressing key issues
such as synchronization across cores and race conditions. This study contributes to the field
by introducing a novel TMR implementation for many-core processors and advancing the
integration of fault tolerance mechanisms in complex computing environments, offering a
robust solution for critical applications.