Islam, Riadul (2011) High-speed Energy-efficient Soft Error Tolerant Flip-flops. Masters thesis, Concordia University.
|PDF - Accepted Version|
Single event upset (SEU) or soft error caused by alpha particles and cosmic neutrons has emerged as a key reliability concern in nanoscale CMOS technologies. The decrease in signal charge due to the reduction of the operating voltage and node capacitance primarily increases the soft error rate (SER) in integrated circuits. The situation is aggravated by the increasing number of memory elements (e.g., flip-flops) on chip, the lack of inherent error masking mechanisms in these elements, and the below-nominal voltage operation for reducing the power consumption. In fact, limiting the power consumption is critical to enhance the battery life of portable electronic devices. In this thesis, I present several soft error tolerant flip-flops that offer high speed while consuming low power either inherently or through low-energy clocking scheme.
The proposed soft error tolerant flip-flops can be divided into two major categories: i) flip-flops with square-wave clock and ii) flip-flops with energy recovery sinusoidal clock, which is very attractive to significantly lower the clock power consumption. The two square-wave clock based proposed flip-flops are: a true single phase clock (TSPC) DICE flip-flop and a clocked precharge soft error robust flip-flop. These flip-flops use fewer transistors and offer as much as 35% lower power-delay-product (PDP) than existing soft error robust pulsed DICE flip-flop. The energy recovery clock based proposed flip-flops are: a soft clock edge SEU hardened (SCESH) flip-flop, C2-DICE flip-flop, a conditional pass Quatro (CPQ) flip-flop, and two energy recovery TSPC flip-flops. These flip-flops exhibit lower PDP ranging from 30% to 69% when compared to the pulsed DICE flip-flop and the single-ended conditional capturing energy recovery (SCCER) flip-flop. Thus, the proposed flip-flops provide a wide range of power and delay choices and as such can be used in a variety of low-power or high performance applications including high-end microprocessors, low-power system-on-chips (SOCs), and implantable medical devices.
|Divisions:||Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering|
|Item Type:||Thesis (Masters)|
|Degree Name:||M.A. Sc.|
|Program:||Electrical and Computer Engineering|
|Date:||26 August 2011|
|Thesis Supervisor(s):||Jahinuzzaman, Shah M.|
|Keywords:||Flip-flop, single event upset, single event transient, soft error, DICE latch, Quatro latch, SERS latch, energy recovery|
|Deposited By:||RIADUL ISLAM|
|Deposited On:||17 Nov 2011 13:59|
|Last Modified:||17 Nov 2011 13:59|
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