Mahran, Sara (2021) Design of a Triple-Mode Low Power Single-Ended Source-Series-Terminated Driver. Masters thesis, Concordia University.
Preview |
Text (application/pdf)
6MBMahran_MASc_S2022.pdf - Accepted Version |
Abstract
In data centers, the multi-mode fiber (MMF) links and vertical cavity surface emitting laser (VCSEL) diode are widely used for short-reach optical communications (< 100 m) because of their low cost and their ability to handle the ever-increasing data rates. In conventional VCSEL drivers, the laser diode driver (LDD) can be bonded to a chip carrier, while the host chip is bonded to another chip carrier. This host chip contains an electrical link driver and is connected to the VCSEL driver via a short electrical link. To reduce the overall power consumption of the conventional VCSEL driver system, the electrical link driver in the host chip can be modified so that it can drive the VCSEL diode directly, eliminating the laser diode driver. Thus, the modified driver can drive either an electrical link or a VCSEL diode. By modifying the packaging, the VCSEL diode can be wire bonded to the host chip and directly driven.
Driving a VCSEL diode requires features such as asymmetric equalization, relatively low modulation current, and DC current source to bias the VCSEL. On the other hand, driving an electrical link requires symmetric equalization, relatively high output voltage swing from the driver, and matched output impedance. Accordingly, a typical electrical link driver cannot drive a VCSEL diode and the VCSEL driver is not suitable for driving an electrical link. The proposed design is a single-ended source-series-terminated (SST) voltage-mode driver in a CMOS 65 nm technology with three driving modes: driving electrical links with losses up to 16 dB (mode I), driving VCSEL diodes through a short electrical link (mode II), and driving VCSEL diodes directly wire bonded to the driver (mode III). The proposed design provides a tunable output swing without changing the driver output impedance and achieves a smooth transition between symmetric and asymmetric equalization as needed. In simulation, the proposed triple-mode driver operates up to a bit rate of 20 Gb/s, and dissipates at most 27.6 mW of power when operating at mode II when using a supply voltage of 1.2 V.
| Divisions: | Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering |
|---|---|
| Item Type: | Thesis (Masters) |
| Authors: | Mahran, Sara |
| Institution: | Concordia University |
| Degree Name: | M.A. Sc. |
| Program: | Electrical and Computer Engineering |
| Date: | 13 December 2021 |
| Thesis Supervisor(s): | Cowan, Glenn and Liboiron-Ladouceur, Odile |
| ID Code: | 990192 |
| Deposited By: | Sara Mahran |
| Deposited On: | 16 Jun 2022 14:50 |
| Last Modified: | 16 Jun 2022 14:50 |
References:
[1] G. Belfiore, M. Khafaji, R. Henker and F. Ellinger, "A 50 Gb/s 190 mW Asymmetric 3-Tap FFE VCSEL Driver," in IEEE Journal of Solid-State Circuits, vol. 52, no. 9, pp. 2422-2429, Sept. 2017.[2] K. T. Ng, Y. B. Choi and K. C. Wang, "A 25Gb/s Common-Cathode VCSEL Driver," 2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2014, pp. 1-4.
[3] A. S. Ramani, S. Nayak and S. Shekhar, "A Differential Push-Pull Voltage Mode VCSEL Driver in 65-nm CMOS," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 11, pp. 4147-4157, Nov. 2019.
[4] H. Choi, J. Hwang, G. Jeong, G. Kim and D. Jeong, "A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver with Series Inductive Peaking in 65-nm CMOS," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 12, pp. 1824-1828, Dec. 2018.
[5] X. Jia, " A High-speed and Low Power Electrical Link Transceiver," M.S. thesis, Gina Cody School of Eng. and Computer Sc. Concordia Univ., Quebec, Canada, 2017. Accessed on: Sep. 1st, 2021. [Online]. Available:https://spectrum.library.concordia.ca/982490/1/Jia_MASc_S2017.pdf.
[6] H. Song, S. Kim, and D.K. Jeong, " A reduced-swing voltage-mode driver for low-power multi-gb/s transmitters, " in Journal of semiconductor technology and science, vol. 9, no. 2, pp. 104-109, June 2009.
[7] X. Wang and P. Gui, "A Hybrid Line Driver with Voltage-Mode SST Pre-Emphasis and Current-Mode Equalization," 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020, pp. 750-753.
[8] B. Dehlaghi and A. C. Carusone, "A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOS," 2015 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 2015, pp. 1-4.
[9] M. Kossel et al., "A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With < -16 dB Return Loss Over 10 GHz Bandwidth," in IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2905-2920, Dec. 2008.
[10] B. Razavi, Design of Integrated Circuits for Optical Communications, 2002.
[11] D. Abdelrahman, " Modeling and Design of High-Speed CMOS Receivers for Short-Reach Photonic Links," Ph.D dissertation, Gina Cody School of Eng. and Computer Sc. Concordia Univ., Quebec, Canada, 2021. Accessed on: Sep. 1st, 2021. [Online]. Available:https://spectrum.library.concordia.ca/988237/1/Abdelrahman_PhD_S2021.pdf
[12] “RO4000® Series High Frequency Circuit Materials”. Accessed on Aug. 31st, 2021 [Online]. Available:https://www.mclpcb.com/wp-content/uploads/2021/05/Rogers-ro4000-laminates-ro4003c-and-ro4350b-data-sheet.pdf
[13] G. Jeong, et al., "A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Architecture Utilizing Constant Gm," 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), Xiamen, China, 2015, pp. 1-4.
[14] M. Raj, M. Monge and A. Emami, "A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS," in IEEE Journal of Solid-State Circuits, vol. 51, no. 8, pp. 1734-1743, Aug. 2016.
[15] K. Kwak, J. Ra, H. Moon, S. Hong and O. Kwon, "A Low-Power Two-Tap Voltage-Mode Transmitter With Precisely Matched Output Impedance Using an Embedded Calibration Circuit," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 6, pp. 573-577, June 2016.
[16] M. M. Khafaji, G. Belfiore, J. Pliva, R. Henker and F. Ellinger, "A 4X45 Gb/s Two-Tap FFE VCSEL Driver in 14-nm FinFET CMOS Suitable for Burst Mode Operation," in IEEE Journal of Solid-State Circuits, vol. 53, no. 9, pp. 2686-2695, Sept. 2018.
[17] H. Meng et al., "Modeling of transfer Characteristics for the broadband power line communication channel," in IEEE Transactions on Power Delivery, vol. 19, no. 3, pp. 1057-1064, July 2004.
[18] M. Shibata and A. C. Carusone, "A 26-Gb/s 1.80-pJ/b CMOS-driven transmitter for 850-nm common-cathode VCSELs," 2015 Optical Fiber Communications Conference and Exhibition (OFC), 2015, pp. 1-3.
[19] S. Mahran, O. Liboiron-Ladouceur and G. Cowan, "20 Gb/s Dual-Mode SST VCSEL Driver," 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, pp. 428-431.
[20] A. Sharif-Bakhtiar and A. Chan Carusone, "A 20 Gb/s CMOS Optical Receiver With Limited-Bandwidth Front End and Local Feedback IIR-DFE," in IEEE Journal of Solid-State Circuits, vol. 51, no. 11, pp. 2679-2689, Nov. 2016.
[21] J. E. Proesel et al., "A 32 Gb/s, 4.7 pJ/bit optical link with −11.7 dBm sensitivity in 14-nm FinFET CMOS," IEEE J. Solid-State Circuits, vol. 53, no. 4, pp. 1214-1226, 2018.
[22] D. Deslandes, "Design equations for tapered microstrip-to-Substrate Integrated Waveguide transitions," 2010 IEEE MTT-S International Microwave Symposium, 2010, pp. 704-707.
Repository Staff Only: item control page
Download Statistics
Download Statistics