Abstract

Over the past two decades and specially more recently, AlGaN/GaN heterojunction field effect transistors (HFETs) have drawn a great deal of attention due to their excellent performance
in high-frequency power amplifiers and RF switches explored in the 5G-LTE applications. Since the ability to operate at high voltages is crucial in delivering both the large RF gain/output power and the high voltage switching capabilities, boosting the already high off-state breakdown voltage (BVoff) of these transistors to much higher values has been of substantial importance. While a number of techniques have already been developed for realization of high breakdown voltage AlGaN/GaN HFETs, in addition to imposing certain challenges to the
fabrication procedure, these techniques impose strain on satisfying high frequency response requirements. Among these techniques, the field-plate (FP) is the most widely used. As an alternative to this mainstream technique, this thesis presents a novel concept of field plating without incorporation of any physical plate. In this approach, I have assessed the suitability of isolation feature geometry and existence of surface states in modifying the profile of the longitudinal electric field, and enhancement of the off-state breakdown voltage. This approach while using a simple fabrication process, is capable of limiting the degradation of the frequency response commonly observed with FP implementation.
In order to explore the limitations of this technique and to formulate guidelines for achieving high BVoff values, I have experimentally and theoretically studied the effects of alternative isolation feature geometries on high voltage device characteristics of AlGaN/GaN
HFETs. According to our explorations on three different categories of isolation features (including conventional mesa, non-slanted fin, and slanted fin), the peak of the electric field at the drain edge of the gate, which is responsible for impact ionization, is reduced as a result of tailoring its profile when a more resistive path is imposed on the drain access region by shrinking the width of the isolation feature geometry. While HFETs realized on fins of smaller widths benefit more from the
depleting effect of acceptor sidewall surface states and consequently a higher BVoff, they suffer from a lower current density in the on-state. The slanted fin isolation feature geometry that I have
proposed, while maintaining high breakdown voltage in the off-state, reduces the resistance in the on-state which is represented by its highest Baliga’s figure of merit (BFOM) among the three categories of isolation feature geometries. In addition, in this thesis I have explored the effect of isolation feature geometry on the reverse gate leakage, which is considered as one of the main problems limiting the full-scale
commercialization of these HFETs. In this exploration, I have studied the significance of room temperature leakage from the top surface gate as well as gated-sidewalls to the 2-D electron gas (2DEG) for a wide range of gate-source voltages (VGS) (i.e. below and above the threshold voltage)and at zero drain-source bias. I have proved that in the explored fin-type HFETs that are sub-micrometer-wide, for all values of VGS leakage through the gated sidewalls is more significant than the leakage from the top surface gate. This is while in the mesa category, the sidewall leakage is of substantial importance only at more positive values of VGS, and leakage from the top surface gate takes over at more negative VGS values. I have demonstrated that the discrepancy in the dominance of the aforementioned leakage paths at more negative VGS values among the explored fin and mesa-type HFETs is due to the larger amount of the electric field across the barrier in the gated region of the mesa-type HFET for this range of VGS.