Abstract

Rising internet traffic from AI and bandwidth-intensive applications has increased the demand
for fast, low-power optical links in modern data centers. Multi-level modulation schemes such as
four-level pulse amplitude modulation (PAM-4) improve spectral efficiency and throughput while
relaxing bandwidth requirements. However, PAM-4 imposes strict linearity demands on the optical
receiver’s analog front-end, particularly the main amplifier.
This thesis presents a highly linear, power-efficient main amplifier for PAM-4 and NRZ optical
receivers, implemented in 65-nm CMOS. The design uses a gm/gm topology with interleaved active
feedback (IAFB) to extend bandwidth without passive inductors. Linearity is further improved by
reducing third-order distortion through resistive voltage dividers at the feedback inverters’ inputs
and by increasing their gain. Post-layout simulations show superior bandwidth, linearity, and ver-
tical eye opening (VEO) compared to a conventional Cherry–Hooper amplifier, including a 67%
reduction in total harmonic distortion (THD) at a 500-mVpp output swing.
To mitigate channel impairments, equalization is integrated directly into the main amplifier by
introducing a pole within the active feedback loop. This removes the need for a separate continuous-
time linear equalizer (CTLE), reducing chip area and power. The proposed amplifier is part of a
four-channel differential optical receiver, fabricated with a total chip area of 2 mm × 1 mm. Post-
layout results indicate 10-Gb/s per-channel operation for both NRZ and PAM-4, with about 30 mW
power consumption per channel.